Cliff Hou, TSMC’s senior vice president and deputy co-chief operating officer, said Taiwanese makers’ share of back-end advanced packaging equipment has passed 20% and reaches as much as 25%, against about 10% of front-end process equipment, Economic Daily News reported from his speech on 11 November at the Chinese National Federation of Industries’ 80th Industry Day.
The same week, AMD announced availability of its 6th Gen EPYC SP7 server processors, codenamed Venice, saying in a 10 November press kit that systems using them are shipping from all leading OEMs and ODMs. Commercial Times reports the chip is made on TSMC’s N2 process with CoWoS-L packaging. AMD’s Data Center segment brought in a record $8.5 billion in the third quarter, about 63% of its $13.4 billion revenue, by our arithmetic from its results filing.
Business Pill · Embedded Dependency
An evergreen Business Engineer explainer on embedded dependency: what is inside what you buy. It explains the general idea only and does not discuss TSMC, AMD or Taiwanese equipment makers.
The key insight: TSMC’s Cliff Hou said Taiwanese makers have passed 20%, and reach as much as 25%, of back-end advanced packaging equipment, against about 10% of front-end process equipment, Economic Daily News reported. AMD’s Data Center segment, whose Venice processor uses TSMC’s 2nm process and CoWoS-L packaging, was about 63% of its record third-quarter revenue, by our arithmetic.
Hou spoke on the challenges and opportunities for the semiconductor industry in the AI wave. AI is pushing advanced packaging, which places higher demands on precision machinery and equipment, he said, and Taiwan’s decades of machinery-making give equipment makers an opening into the chip industry, according to Economic Daily News.
He also flagged a gap. Taiwan’s back-end equipment makers are still short on software and system integration, and international equipment makers have seen the opportunity and are moving faster in Taiwan, the paper reported. The Taiwan Semiconductor Industry Association and ITRI run a programme pairing software companies with equipment makers.
Hou put this year’s global semiconductor output above US$1.6 trillion, possibly reaching US$1.7 trillion, and semiconductors at about 13% of Taiwan’s GDP, the reports say.
Share of chipmaking equipment made by Taiwanese companies, as TSMC’s Cliff Hou described it on 11 November 2026: 20% to 25% of back-end advanced packaging equipment, against about 10% of front-end process equipment in the Economic Daily News account, or a self-made rate below 1% in the TechNews account, which gives the 20% to 25% as a share of TSMC’s back-end purchases. Sources: Economic Daily News, United Daily News, TechNews.
Two Accounts of the Same Remark
The outlets frame the number differently. United Daily News compares the back end with a Taiwanese share of about 10% in front-end process equipment. TechNews gives the front-end self-made rate as below 1% and says that, taking TSMC as the example, Taiwan-made equipment is 20% to 25% of its back-end advanced packaging purchases.
So one account is an industry manufacturing share and the other is TSMC’s own purchasing mix. Both put the back end at 20% to 25%. On the Economic Daily News comparison, that is two to two-and-a-half times the front-end share, by our arithmetic. TechNews also reports a global opportunity of up to US$50 billion for equipment makers.
Where AMD’s Venice Fits
AMD said on 21 May that Venice was ramping production in Taiwan on TSMC’s 2nm process, with plans to ramp at TSMC Arizona later. Its release says Venice is “the first high-performance computing (HPC) product in the industry to enter production on TSMC’s advanced 2nm process technology”.
The same release lists TSMC’s SoIC-X and CoWoS-L packaging as used across AMD’s broader AI and data center portfolio. Commercial Times reports that Venice uses CoWoS-L, that the SP8 version for enterprises is due in the first half of 2027, and that Verano, on the enhanced N2P process, and Venice-X are scheduled for the second half.
Commercial Times also reports that AMD announced in May an investment of more than US$10 billion in Taiwan’s industrial ecosystem, with ASE and SPIL working on wafer-level bridge interconnects and Powertech on a panel-level version. On the 3 November earnings call, Lisa Su said revenue shipments of Venice began in the third quarter, as we reported at the time.
The Demand Behind the Packaging
AMD’s Data Center segment revenue was a record $8.5 billion in the third quarter, up 97% year over year, against total revenue of $13.4 billion, the filing says. That is about 63% of revenue, by our arithmetic. Lisa Su said in the release: “we expect growth to accelerate further in the fourth quarter as we scale Helios and ‘Venice’ production”.
At its In Depth forum, AMD estimated the data center CPU market at about US$26 billion in 2025, rising to about US$220 billion in 2030, Commercial Times reports. That is about 8.5 times, by our arithmetic. TSMC’s other executives were upbeat on demand the same day, as we covered on 11 November.
The Structural Read
As we read it, the remark places Taiwan’s equipment makers in the part of chipmaking that AI demand is stretching, packaging, rather than in the front-end fab tools where their share is far smaller. Hou also named the gap, software and system integration, and said international equipment makers are moving faster in Taiwan.
Lisa Su, chair and CEO, AMD, release, 21 May 2026
“Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment.”
Three Implications
FOR TAIWANESE TOOLMAKERS Hou said they still lack software and system integration, and that the Taiwan Semiconductor Industry Association and ITRI run a programme pairing them with software companies, Economic Daily News reported.
FOR AMD Commercial Times reports that Venice SP8 is due in the first half of 2027, with Verano on N2P and Venice-X in the second half.
FOR THE NUMBERS The 20% to 25% comes from reports of a speech, not a TSMC document; the outlets differ on whether it is an industry share or TSMC’s purchasing mix.
The framework says of Layer 2, Foundries & Packaging: “Allocation power at the foundry is now more consequential than chip design itself.”
As we read it, Hou’s figure shows Taiwanese suppliers taking a larger share of the tools inside that layer’s packaging half than of its front-end fabs. The framework predates his speech and does not discuss it.
AMD revenue by segment in the third quarter of 2026: Data Center a record $8.5 billion, Client and Gaming $3.7 billion and Embedded $1.1 billion, of $13.4 billion in total; the 63% share is our arithmetic and the segments sum to $13.3 billion on rounding. Source: AMD third-quarter 2026 results, Form 8-K Exhibit 99.1.
What Is Not Established
We read news reports of Hou’s speech, not a transcript or slides, and TSMC has not published the figures. The reports differ on the front-end comparison, about 10% or below 1%, and on whether the 20% to 25% describes the industry or TSMC’s purchases. No source names the Taiwanese equipment makers or gives the equipment spending in dollars.
AMD’s press kit says systems are shipping but, like the other AMD documents we read, gives no Venice unit or revenue figure.
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TSMC’s Cliff Hou said Taiwanese makers now supply 20% to 25% of back-end advanced packaging equipment, against about 10%, or below 1% in one account, of front-end tools, as AMD’s 2nm Venice, packaged with CoWoS-L, ships. AMD’s Data Center segment was about 63% of its record third quarter, by our arithmetic.
A note on sourcing. Cliff Hou’s remarks come from Chinese-language reports of his 11 November speech by Economic Daily News, United Daily News and TechNews, which we read in full and translated ourselves; we did not see a transcript or slides and did not contact TSMC or AMD. The Venice availability comes from AMD’s 10 November press kit, and the packaging and roadmap details from Commercial Times and AMD’s 21 May release; the revenue figures come from AMD’s third-quarter results filed with the SEC. Shares and ratios are our arithmetic.
Gennaro Cuofano is a CRO and tech executive who has worked in AI since late 2015, starting with bringing NLP, natural-language generation, voice and chatbot products to the marketing industry. His background is in law and finance: he holds a Master's degree in Law and an International MBA with an emphasis on corporate finance (LUISS Business School and the University of San Diego, 2012), and worked as a financial analyst at a real-estate investment firm in San Diego and as an assistant controller. His work focuses on business model strategy, business engineering and, more broadly, structural analysis: how companies make money, read from their own filings. He created FourWeekMBA and leads research there and at The Business Engineer, his newsletter on AI and business strategy, with over 95,000 subscribers and more than 1,000 published analyses. His writing has also appeared on Entrepreneur (for example, How to Digitize a Family Business in Europe) and HackerNoon. Find him on LinkedIn and Substack. See how we source.
