CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s advanced packaging service that mounts several chips, typically an AI processor and stacks of high-bandwidth memory (HBM), side by side on a silicon interposer that wires them together, then attaches the assembly to a substrate. TSMC lists CoWoS among its 3DFabric services for joining different chips into one high-performance package. It matters because an AI accelerator is not finished until it is packaged with its memory, so packaging capacity, not only wafer capacity, sets how many AI chips reach the market.
How CoWoS works
What changed in 2025-26
High performance computing, which includes AI accelerators, rose from 43% of TSMC’s net revenue in 2023 to 58% in 2025. In the third quarter of 2026 TSMC’s revenue was $46.72 billion, up 41.2% year on year, and it guided to $52.3-54.3 billion for the fourth quarter.
TSMC’s annual report says its 2025 capital expenditures included expanding capacity for specialty technologies and advanced packaging, including building and facility expansion for Fab 23 and Fab 24.
In October 2024 Amkor and TSMC signed a memorandum of understanding under which TSMC will contract turnkey advanced packaging and test services from Amkor’s planned facility in Peoria, Arizona; the companies named InFO and CoWoS as technologies to be used.
SK hynix said in April 2024 it would invest an estimated $3.87 billion in West Lafayette, Indiana, in an advanced packaging plant and R&D facility for HBM, with mass production planned for the second half of 2028.
CoWoS and related packaging pieces
What it means for you
- Investors: track packaging capacity as closely as wafer capacity; an AI chip that cannot be packaged cannot ship.
- Buyers of AI compute: ask suppliers where their accelerators are packaged and how much packaging is contracted, not only which node they use.
- Chip designers: plan for a multi-die package early; interposer size and memory stack count shape cost and delivery.
- Policy watchers: count packaging sites, such as Amkor in Arizona and SK hynix in Indiana, when judging how much of the AI supply chain has moved.
- Read TSMC's platform mix each quarter; the share from high performance computing is the cleanest proxy for AI demand at the foundry.
CoWoS shows that the AI bottleneck moves: first GPUs, then the step that joins processors to memory. The Business Engineer reads packaging as a toll point where TSMC earns a second time on the same chip, and where new capacity in the US and from memory makers is now being built.
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Frequently asked questions
What does CoWoS stand for?
Chip-on-Wafer-on-Substrate: chips are placed on a silicon interposer wafer, which is then mounted on a package substrate.
Why is CoWoS important for AI chips?
It joins the AI processor with stacks of high-bandwidth memory in one package; without that step the accelerator cannot be finished.
Who makes CoWoS?
TSMC offers CoWoS as one of its 3DFabric advanced packaging services; under a 2024 agreement Amkor will provide turnkey packaging and test for TSMC customers in Arizona.
How much of TSMC's revenue comes from AI-related chips?
High performance computing, which includes AI accelerators, was 58% of TSMC's net revenue in 2025, up from 43% in 2023.
Sources
- TSMC (2026), Annual report on Form 20-F for fiscal 2025
- TSMC (2026), TSMC Reports Third Quarter EPS of NT$29.43, Form 6-K, 15 October 2026
- Cho et al. (2016), Signal and Power Integrity Design of 2.5D HBM on Si Interposer
- SK hynix (2024), SK hynix Signs Investment Agreement of Advanced Chip Packaging with Indiana, 3 April 2024
- Amkor (2024), Amkor and TSMC to Expand Partnership and Collaborate on Advanced Packaging in Arizona, 3 October 2024
The full guide
The complete explainer, cleaned up and reformatted for mobile.
Even when logic and memory exist, GPUs cannot be completed without advanced packaging.
Why CoWoS Is Critical
- Enables GPU + HBM integration on single package
- Without CoWoS, chips are built but cannot be finished
Supply Chain Response
- SK hynix US plant (Indiana): an estimated $3.87 billion advanced packaging plant and R&D facility for HBM, announced in April 2024, with mass production planned for the second half of 2028
Focus: Keep advanced nodes in-house. Reduces TSMC dependency.
This is part of a comprehensive analysis. Read the full analysis on The Business Engineer.










