Marvell announced the second-generation Structera X 3406 and 3506 CXL memory expanders on 12 October 2026, and says the 3406 supports up to 9TB of DDR4 memory per controller. In its press release, Marvell says the two chips add six DDR4 or DDR5 channels, 50% more than the previous generation, with PCIe Gen 6 connectivity.
Marvell says the Structera X 3406 and 3506 are expected to sample in Q1 2027, and that they extend the Structera X 2404 and 2504 architecture already shipping to hyperscalers.
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The key insight: As we read it, Marvell is selling memory capacity as a fix for inference: its release says AI inference is memory bound, and the new chips add channels, cross-host sharing and compression to give servers more usable memory.
Marvell describes the chips as memory expansion controllers for cloud, enterprise and AI servers. Its release says the 3406 supports up to 18 DDR4 RDIMM slots and 9TB, and the 3506 up to 12 DDR5 RDIMM slots and 6TB.
The release says the chips can share memory capacity with up to four hosts, with up to 256GB/s of host bandwidth over PCIe 6.0 x16. Marvell calls both the six-channel design and the four-host connectivity industry firsts.
Marvell says inline LZ4 compression now runs at up to 250GB/s, five times the previous generation’s throughput, and unlocks up to 2–3x more effective memory capacity, depending on workloads.
Structera X 3406/3506 against Marvell’s first generation, as Marvell states it on 12 October 2026: five times the LZ4 compression throughput, up to twice the supportable context window at equal latency, and 50% more memory channels. These are Marvell’s claims.
Why Marvell Says Inference Needs It
The release argues that modern AI inference workloads, from LLM serving to deep learning recommendation models, are memory bound, and that KV-cache capacity directly determines time to first token, throughput and XPU utilisation.
For LLM serving, Marvell says Structera X delivers up to 40–50% faster time to first token at equivalent context length, or up to 2x longer supportable context windows at equivalent latency, compared with the previous generation. For recommendation models, it claims up to 2x higher queries per second, without saying in the release what that is compared against.
Will Chu, Marvell’s executive vice president and general manager for Custom Cloud Solutions, said the controllers were “co-developed with leading hyperscalers to address the most demanding AI infrastructure requirements.”
The Memory-Shortage Angle
The release quotes Jim Handy, general director of Objective Analysis, who links CXL to memory prices: “today’s memory shortage and subsequent high prices are driving IT managers to use CXL to re-deploy used DDR4 DIMMs into DDR5 systems for immediate cost savings.”
Handy also said that managers will use CXL’s memory pools to reduce stranded memory, and will find controllers that offer compression “to be even more interesting.” Memory bandwidth was also central to Microsoft’s Maia 300 announcement the same day, and Nvidia’s move into the HBM base die, which we covered on 10 October.
Who Is Quoted
Beyond Marvell and the analyst, the release carries statements from AMD, Arm, Alibaba, Samsung Electronics and SK hynix. AMD’s Raghu Nambiar said the collaboration builds on AMD EPYC processors, and Arm’s Eddie Ramirez said the controllers bring CXL 3.2, memory expansion and compression to the Arm ecosystem.
Samsung and SK hynix describe pairing Structera with their memory. Marvell says it will show the chips at its booth at the OCP Global Summit in San Jose, 12–15 October. Marvell’s data-centre forecasts were the subject of our 6 October piece.
The Structural Read
As we read it, the case Marvell makes runs through the KV cache: the release says KV-cache capacity directly determines time to first token, throughput and XPU utilisation.
As we read it, compression is the lever that multiplies the hardware: Marvell says inline LZ4 at up to 250GB/s unlocks up to 2–3x more effective capacity, depending on workloads.
As we read it, the analyst quote adds a cost angle the specifications do not: Jim Handy links CXL to reusing older DDR4 memory while memory prices are high.
Jim Handy, Objective Analysis, in Marvell’s 12 October 2026 release
“today’s memory shortage and subsequent high prices are driving IT managers to use CXL to re-deploy used DDR4 DIMMs into DDR5 systems for immediate cost savings.”
Three Implications
HYPERSCALERS Marvell says the first-generation Structera X 2404 and 2504 are already shipping to hyperscalers, and that the new controllers were co-developed with leading hyperscalers.
MEMORY MAKERS The release quotes Samsung and SK hynix on pairing Structera with their memory.
SERVER BUILDERS Marvell says the 3406 and 3506 are expected to sample in Q1 2027.
The framework puts it this way: “The AI race has a new bottleneck, and it’s not what most observers expect.”
As we read it, Marvell’s release makes the same argument from the server side: it says memory is a critical constraint of AI performance and infrastructure efficiency.
Who is quoted in Marvell’s 12 October 2026 release: AMD, Arm, Alibaba, Samsung, SK hynix and the analyst firm Objective Analysis. These are statements; the release names no customer for the new chips.
What Is Not Established
Every capability, ‘industry-first’ label and performance figure here is Marvell’s claim, the LLM-serving and compression comparisons are against Marvell’s own previous generation, and the release does not state the baseline for its recommendation-model figures. The release gives no price and names no customer for the new chips, and sampling in Q1 2027 is an expectation. We have seen no independent test.
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Marvell says its second-generation Structera X chips add six memory channels, support up to 9TB of DDR4 or 6TB of DDR5 per controller and can share memory across up to four hosts. It expects them to sample in Q1 2027.
A note on sourcing. On 12 October 2026 we read Marvell’s press release in full. Every capability, ‘industry-first’ label and performance figure here is Marvell’s claim, and Q1 2027 sampling is Marvell’s expectation; we have not seen independent tests. Nothing here is investment advice.
Gennaro Cuofano is a CRO and tech executive who has worked in AI since late 2015, starting with bringing NLP, natural-language generation, voice and chatbot products to the marketing industry. His background is in law and finance: he holds a Master's degree in Law and an International MBA with an emphasis on corporate finance (LUISS Business School and the University of San Diego, 2012), and worked as a financial analyst at a real-estate investment firm in San Diego and as an assistant controller. His work focuses on business model strategy, business engineering and, more broadly, structural analysis: how companies make money, read from their own filings. He created FourWeekMBA and leads research there and at The Business Engineer, his newsletter on AI and business strategy, with over 95,000 subscribers and more than 1,000 published analyses. His writing has also appeared on Entrepreneur, HackerNoon and Search Engine People. Find him on LinkedIn and Substack. See how we source.
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