Nvidia’s NVHBM, announced on 26 August 2026, moves Nvidia’s custom memory controller off the accelerator die and into the HBM base die, a base die that the Korean trade outlet TheElec reports TSMC will make for Micron. Nvidia says that delivers up to 30% more memory bandwidth and 15% lower HBM power than standard HBM4E.
On 30 September 2026, Micron added the manufacturing side. On its post-earnings analyst call, Micron’s Scott DeBoer said its HBM4E base die, for both the custom NVHBM product and the JEDEC-specified one, is on a foundry process rather than the in-house base die Micron uses on HBM4. TheElec reports that the foundry is TSMC.
Nvidia presented NVHBM as an expansion of NVLink Fusion, its programme for connecting custom accelerators, which it calls XPUs, to its rack-scale platform. Its blog says NVHBM will be validated and offered by leading memory partners and extended to NVLink Fusion customers.
The blog says traditional HBM places the memory controller on the XPU die, using silicon that could otherwise go to compute. NVHBM, it says, integrates Nvidia’s custom memory controller into the HBM base die, and is built on the same technology Nvidia will use for future GPUs.
Against standard HBM4E, Nvidia states up to 30% greater memory bandwidth, 15% lower HBM power consumption and up to 25% more area freed on the XPU compute die. It says it is establishing a standard NVHBM implementation available from multiple memory providers.
Nvidia named Amazon’s Annapurna Labs as the first to work on NVHBM. The blog says Annapurna will support NVLink Fusion with its next-generation Trainium chips, starting with Trainium4.
Nvidia’s own “up to” figures for NVHBM against standard HBM4E, from its 26 August 2026 technical blog. The four are different measures and do not add up; we have not seen independent measurements.
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A one-minute explainer of the memory wall: why moving data to and from memory, not raw compute, often limits AI chips. It teaches the general idea only and says nothing about any company in this story.
The key insight: As we read it, the two companies describe one design from two ends: Nvidia says NVHBM puts its memory controller in the HBM base die, and Micron says its HBM4E base die, custom and standard, is made on a foundry process rather than in-house. The performance figures are Nvidia’s own “up to” claims.
How Nvidia Says It Works
The technical blog attributes the area saving mainly to a redesigned physical memory interface, or PHY. It says NVHBM uses a custom base die with the memory controller moved into the 3D HBM stack and a custom PHY integrated.
Compared with the JEDEC HBM4e standard, the technical blog says this design reduces PHY and support area by up to 67%, and that the narrower interface provides up to 80% more usable silicon across the entire layout.
On power, it gives a worked example: across a 1-gigawatt data center using 2,000W XPUs, the HBM power saving can enable up to 15,000 additional XPUs in compute headroom. Combining the bandwidth, area and power figures, Nvidia says the result is a 30% overall end-to-end performance increase per XPU.
What Micron Said on 30 September
Asked about the competitiveness of its base die on HBM4E, DeBoer, Micron’s president and chief technology and products officer, answered: “On HBM4E, we have co-designed with NVIDIA, but not in-house base die like we use on HBM4.”
He continued: “On HBM4E, this co-design is on a foundry process, both for the customized product and for the JEDEC-specified product.” He said Micron’s differentiation would remain in power, speed performance and margin.
Earlier on the call he described the work with Nvidia as “the first major custom HBM product out in the market”, adding: “And we’ve been working with NVIDIA for over a year on HBM4E, what’s called NV HBM.”
Chief operating officer Manish Bhatia said: “as we look at the NV HBM with customization, we do expect that to be a high-value product as well.”
Where the memory controller sits, per Nvidia’s 26 August 2026 posts, and who makes the base die, per Micron’s 30 September 2026 call. Micron says “a foundry process”; the TSMC attribution is TheElec’s reporting.
Where TSMC Comes In
In the transcript we read, Micron refers to “a foundry process” without naming the foundry. TheElec, reporting on the call on 1 October 2026, writes that Micron is outsourcing production of the HBM4E base die to TSMC, that the die is believed to be based on a 3-nanometer-class process, and that the NVHBM base die will use the same approach.
TheElec also reports that Micron will make the HBM4E core dies on its own 1-gamma DRAM process. The TSMC attribution and the process detail are TheElec’s reporting; we have not seen them in a Micron or Nvidia document.
The Structural Read
Nvidia’s technical blog says the area saving comes mainly from moving the memory controller into the 3D HBM stack and integrating a custom PHY, which it says cuts PHY and support area by up to 67% against the JEDEC HBM4e standard.
Micron’s DeBoer drew the line between generations on the call: HBM4 uses Micron’s in-house base die, while on HBM4E the co-design with Nvidia is on a foundry process for both the customized and the JEDEC-specified product.
As we read it, that puts a logic-process part at the bottom of the memory stack, designed with Nvidia and, per TheElec’s reporting, made by TSMC, while Micron says its differentiation stays in power, speed performance and margin.
Scott DeBoer, Micron, on the company’s fourth-quarter fiscal 2026 post-earnings analyst call (30 September 2026)
“On HBM4E, this co-design is on a foundry process, both for the customized product and for the JEDEC-specified product.”
Three Implications
CUSTOM ACCELERATOR BUILDERS Nvidia says NVHBM is offered to NVLink Fusion customers through a standard implementation from multiple memory providers, with Amazon’s Annapurna Labs the first to work on it.
MEMORY MAKERS Micron says it has worked with Nvidia for over a year on what it calls NV HBM, and its chief operating officer says it expects a high-value product.
FOUNDRIES Micron says the HBM4E base die is on a foundry process; TheElec reports that the foundry is TSMC and that the die is believed to be 3-nanometer-class.
The analysis puts it this way: “Memory is becoming the new compute. HBM growth is outpacing accelerator demand, making memory the rate-limiting factor in the AI scaling equation.”
As we read it, NVHBM follows that line at the package level: Nvidia moves a compute-side function, the memory controller, into the memory stack, and Micron says the base die that holds it is made on a foundry process.
What Is Not Established
The two Nvidia posts we read, dated 26 August 2026, do not name memory partners other than describing them as leading memory partners, and give no availability date or price. Every performance figure here is Nvidia’s own “up to” claim; we have not seen independent measurements.
The Micron transcript we read says “a foundry process” and does not name TSMC. We have not read Micron’s separately published prepared remarks for the quarter.
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A Business Engineer analysis of high-bandwidth memory as the binding constraint on AI scaling.
Nvidia says NVHBM moves its memory controller into the HBM base die and, against standard HBM4E, delivers up to 30% more bandwidth and 15% lower HBM power, with Amazon’s Annapurna Labs first to work on it. On 30 September 2026 Micron said its HBM4E base die, custom and standard, is on a foundry process, and TheElec reports that the foundry is TSMC.
A note on sourcing. We read Nvidia’s two NVHBM posts of 26 August 2026 and the HBM4E exchanges in the transcript of Micron’s 30 September 2026 analyst call in full on 10 October 2026. Every performance figure is Nvidia’s own; the TSMC detail is TheElec’s reporting, which we label as such. Nothing here is a forecast, and nothing here is financial or investment advice.
Gennaro Cuofano is a CRO and tech executive who has worked in AI since late 2015, starting with bringing NLP, natural-language generation, voice and chatbot products to the marketing industry. His background is in law and finance: he holds a Master's degree in Law and an International MBA with an emphasis on corporate finance (LUISS Business School and the University of San Diego, 2012), and worked as a financial analyst at a real-estate investment firm in San Diego and as an assistant controller. His work focuses on business model strategy, business engineering and, more broadly, structural analysis: how companies make money, read from their own filings. He created FourWeekMBA and leads research there and at The Business Engineer, his newsletter on AI and business strategy, with over 95,000 subscribers and more than 1,000 published analyses. His writing has also appeared on Entrepreneur, HackerNoon and Search Engine People. Find him on LinkedIn and Substack. See how we source.
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