SemiAnalysis posted a photograph of the logic die inside Huawei’s Kirin 9050 Pro on 5 November, from its Teardown Lab. Its post describes “Huawei’s Kirin 9050 Pro hybrid-bonded logic die”, and the text on its image calls the processor “Huawei’s two-die LogicFolding chip”.
The image says SemiAnalysis is sharing floor plans, package and transistor-level data, with a full breakdown to follow. The chip also runs Huawei’s on-device AI model, which activates about 6.7% of its parameters at a time against 20% for Apple’s, by our arithmetic from the model sizes Notebookcheck reports.
Business Pill · Concentration
A one-minute explainer of concentration: what happens when a large share of something depends on one supplier, customer or place. It teaches the general idea only and does not discuss Huawei or this chip.
The key insight: SemiAnalysis has posted a teardown photograph of the Kirin 9050 Pro’s logic die and calls it Huawei’s two-die LogicFolding chip; Geekerwan’s teardown, as Notebookcheck reported it, found two dies joined by copper-to-copper hybrid bonding, and the on-device model Notebookcheck describes activates about 6.7% of its parameters at a time against 20% for Apple’s, by our arithmetic.
The post reads: “A silicon face to face: Huawei’s Kirin 9050 Pro hybrid-bonded logic die, direct from SemiAnalysis’ Teardown Lab.”
The graphic attached to it opens with the line “No EUV? No problem!” and adds “Can’t shrink it? Fold it.” It labels the photograph “Logic die shown” and says: “We’re sharing floor plans, package, and transistor-level data.” A line at the bottom reads “FULL BREAKDOWN SOON”.
The image shows a single die. SemiAnalysis’s post gives no performance figures, and its full breakdown had not been published when we read the post.
Active parameters as a share of the total for the on-device mixture-of-experts models Notebookcheck reports: Huawei’s 30B-A2B on the Kirin 9050 Pro and Apple’s 20B-A4B. The shares are our arithmetic.
What Was Posted on X
A silicon face to face: Huawei’s Kirin 9050 Pro hybrid-bonded logic die, direct from SemiAnalysisโ Teardown Lab.
SemiAnalysis posted at 05:00 UTC on 5 November: โA silicon face to face: Huawei’s Kirin 9050 Pro hybrid-bonded logic die, direct from SemiAnalysis’ Teardown Lab.โ The image attached to the post calls the processor Huaweiโs two-die LogicFolding chip and says a full breakdown is coming. This piece uses the post as its starting point.
How the Two Dies Work
Notebookcheck reported on 3 October on a teardown by the Chinese channel Geekerwan. It says the Kirin 9050 Pro “has two dies stacked and joined by copper-to-copper hybrid bonding, which links their metal layers.”
According to that report, Geekerwan identifies the compute die as SMIC N+3 and the secondary die, which holds the cache, I/O interfaces and PLLs, as SMIC N+2. Notebookcheck adds: “Neither Huawei nor SMIC has confirmed the nodes directly.”
Geekerwan counts about 80,000 through-silicon vias connecting the chip to the substrate, the report says, and their keep-out zones consume about 8% of the bottom die’s usable area.
Notebookcheck says each major block spans both dies. In the prime core, most execution units sit on the top die while the L1 and L2 caches sit on the bottom die, directly beneath the load and store units.
The outlet King of Computer Media (KOCPC) cites a paper Huawei presented at ISCAS 2026: at the same process node and the same 1.1V voltage, the big core’s frequency rose from 2.75GHz to 3.1GHz. KOCPC says the bonding pitch shown in the paper reached 1.5 microns, and describes the approach as finer-grained than AMD’s X3D stacked cache or Intel’s Foveros chiplets.
What Huawei Claims
KOCPC reports that Huawei executive director Yu Chengdong unveiled the Kirin 9050 Pro at the HarmonyOS 7 and Mate XT 2 launch event in Guangzhou. It says official data shows the Mate XT 2 with the chip offers 42% higher overall performance than the previous generation.
The South China Morning Post, publishing on 8 September, gives the same 42% figure in a photo caption, “according to Huawei”. Its first paragraph says the processor is serving as a high-stakes test of whether Huawei can bypass US technology sanctions by layering circuits on top of each other, according to analysts.
Notebookcheck names the chip as the SoC in the Mate 90 Pro Max.
The On-Device AI Angle
The neural processing unit gets the largest change, according to Notebookcheck’s account of the teardown: its combined area across both dies is 150% larger than the Kirin 9030 Pro’s. Geekerwan measured 68 TOPS of INT8 throughput and a threefold prefill improvement with a 3B-parameter model, the report says.
Notebookcheck says phones with the chip support an on-device 30B-A2B mixture-of-experts model, with 30 billion parameters and 2 billion active at a time, and that Apple uses a 20B-A4B model. It adds: “The NPU still trails the latest competitors, so Huawei only activates a smaller share of the parameters compared to Apple’s solution.”
On those figures, Huawei’s model activates about 6.7% of its parameters at a time and Apple’s 20%, by our arithmetic (2 of 30, and 4 of 20): Apple’s share is about three times Huawei’s.
Connecting the Coverage
Our related pieces on Huawei and China’s chip supply:
As we read the reports, the design moves part of the gain from the process node to the package: Notebookcheck reports that each major block spans both dies, and KOCPC reports a frequency rise at the same node in Huawei’s paper.
As we read SemiAnalysis’s post, its contribution so far is an independent lab image rather than new numbers: the post gives no performance figures, and its full breakdown is still to come.
As we read the model figures, the AI angle sits in the NPU: Notebookcheck links Huawei’s smaller active share, about 6.7% against 20% for Apple’s model by our arithmetic, to an NPU it says still trails the latest competitors.
Notebookcheck, 3 October 2026
“The Kirin 9050 Pro instead has two dies stacked and joined by copper-to-copper hybrid bonding, which links their metal layers.”
Three Implications
FOR THE TEARDOWN RECORD Notebookcheck reports about 80,000 through-silicon vias and says their keep-out zones consume about 8% of the bottom die’s usable area.
FOR THE PROCESS NODES Notebookcheck reports Geekerwan’s identification of SMIC N+3 and N+2, and says neither Huawei nor SMIC has confirmed the nodes directly.
FOR ON-DEVICE AI Notebookcheck reports an NPU 150% larger in combined area than the Kirin 9030 Pro’s and 68 TOPS of INT8 throughput in Geekerwan’s measurement.
The framework says: “It’s a fundamental constraint on the speed of AI transformation, and it’s creating geopolitical leverage that operates independently of who has the best models.”
As we read it, a chip built around a lithography limit is that idea at the level of one processor: the constraint shapes the design. The framework predates this teardown and does not discuss Huawei’s chip.
What Is Not Established
SemiAnalysis’s full breakdown was not published when we read its post; we read the post and the text on its image only.
The process nodes are Geekerwan’s identification, as reported by Notebookcheck, which says neither Huawei nor SMIC has confirmed them. The 42% figure is Huawei’s claim. We have not read the ISCAS paper or watched Geekerwan’s video; the paper’s figures come from KOCPC’s account. We read the South China Morning Post’s headline, standfirst, photo caption and first paragraph only.
The sources we read give no production volumes or packaging yields for the chip.
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SemiAnalysis’s photograph adds an independent lab’s die image to a design Huawei unveiled in September and Geekerwan took apart, as Notebookcheck reported on 3 October: two dies joined by hybrid bonding, with logic and cache split between them. This week we also covered a report that DeepSeek V5 shifted pretraining to Huawei Ascend chips, and smuggled HBM prices.
A note on sourcing. SemiAnalysis’s post and the text on its image were read on 5 November 2026. The teardown details are Geekerwan’s, as reported by Notebookcheck on 3 October; the ISCAS 2026 paper figures are as reported by KOCPC; the South China Morning Post was read in its opening only. The shares are our arithmetic.
Gennaro Cuofano is a CRO and tech executive who has worked in AI since late 2015, starting with bringing NLP, natural-language generation, voice and chatbot products to the marketing industry. His background is in law and finance: he holds a Master's degree in Law and an International MBA with an emphasis on corporate finance (LUISS Business School and the University of San Diego, 2012), and worked as a financial analyst at a real-estate investment firm in San Diego and as an assistant controller. His work focuses on business model strategy, business engineering and, more broadly, structural analysis: how companies make money, read from their own filings. He created FourWeekMBA and leads research there and at The Business Engineer, his newsletter on AI and business strategy, with over 95,000 subscribers and more than 1,000 published analyses. His writing has also appeared on Entrepreneur (for example, How to Digitize a Family Business in Europe) and HackerNoon. Find him on LinkedIn and Substack. See how we source.
