Tohoku University and Toyota-supplier Aisin built a 16 nm AI chip (SoC) with 32 MB of embedded STT-MRAM that holds both a compact Linux boot image and Tiny YOLOv3 (object detection AI model) weights on-chip.
No external DRAM or SSD is needed for startup or inference. It boots in 65.7 milliseconds (39ร faster) and runs object detection at ~50.7 mJ/frame with big energy savings. They used weight sharing and hybrid 8/16-bit math to fit the model.
The chip also includes on-chip SRAM (used for feature maps and other working data) and a DDR interface, so external memory can still be attached when larger models or more capacity are needed. TSMC manufactures the chip.
Nice real-silicon demo of near-memory computing for edge AI โ useful for automotive cameras, sensor fusion, and always-ready devices that need instant-on and low standby power. Not revolutionary: Others โ Hailo, Ambarella, Renesas, etc. โ already use large on-chip SRAM, embedded MRAM, or in-package DRAM, but itโs a good example of the gains when OS + model live in non-volatile on-chip memory. $TSM $AMBA #Hailo #Renesas #semiconductors
Semiconductor writer Dan Nystedt posted the Tohoku University and AISIN chip on X on 3 November: 32MB of embedded STT-MRAM holding a compact Linux boot image and Tiny YOLOv3 weights, a 65.7 ms boot and about 50.7 mJ per frame. He calls it a real-silicon demo of near-memory computing for edge AI but ‘Not revolutionary’, noting that Hailo, Ambarella and Renesas already use large on-chip SRAM, embedded MRAM or in-package DRAM. We checked his figures against Tohoku University’s release; the release does not name the foundry he gives (TSMC).
A 16nm AI chip from Tohoku University and Toyota group parts maker AISIN boots its operating system 65.7 milliseconds after power-on, 38.59 times faster than a conventional design, Tohoku University said on 2 November. The OS and the AI model’s weights sit in 32MB of embedded STT-MRAM on the chip, not in external DRAM and an SSD.
The chip runs Tiny YOLOv3 object detection at 50.7 mJ per frame, which the university puts at 1/50 of the conventional energy. By our arithmetic, 81% of the conventional design’s 3,129.9 milliseconds from power-on to a first detection was spent booting the OS, not running the AI.
The key insight: As we read the reported figures, the memory, not the accelerator, set the wait: 81% of the conventional design’s 3,129.9 milliseconds from power-on to a first detection was the OS boot, by our arithmetic, and the chip’s 38.59 times boot gain comes from keeping the OS and the model in on-chip MRAM.
What Tohoku and AISIN Built
The system-on-chip, which the university calls a world first, is built on a 16nm FinFET process. Mynavi TECH+ reports that it combines a dual-core Arm Cortex-A53 CPU, an Arm Mali-G31 GPU, an AI accelerator and 32MB of on-chip STT-MRAM, a non-volatile memory that keeps its data with the power off.
The MRAM holds two things: the boot data for the OS and the weights of the AI model. According to the release, that removes the need to move large amounts of data from an external SSD or DRAM at power-on. Mynavi describes the conventional sequence: initialise DRAM, then copy the bootloader and the model from an SSD.
Tohoku calls the design near-memory computing: the accelerator reads weights straight from the MRAM next to it. The university says the paper is being presented at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2026, held in Hsinchu, Taiwan, from 1 to 4 November. Part of the work was funded by NEDO, Japan’s state technology agency.
Time from power-on to a first object detection: OS boot plus one Tiny YOLOv3 AI processing run, for a conventional design with external DRAM and SSD and for the Tohoku University/AISIN chip with 32MB of embedded STT-MRAM. Boot and AI times: Tohoku University release (2 Nov 2026) and Mynavi TECH+. Totals and the 81% share are our arithmetic.
Where the Three Seconds Went
Mynavi gives the baselines behind the release’s multiples. Power-on to OS boot fell from 2,535.3 milliseconds to 65.7. AI processing time for object detection fell from 594.6 milliseconds to 58.5, a 10.16 times cut that the release attributes to removing the transfer of weights from external memory.
Added together, that is 3,129.9 milliseconds for the conventional design and 124.2 milliseconds for the new chip, by our arithmetic. The ratio, 25.2 times, matches the whole-system figure in the release. About 3 seconds disappear from every cold start, also our arithmetic.
In the conventional design, the OS boot took 81% of the time and the AI work 19%, by our arithmetic. On the new chip the boot is down to 53% of a much shorter total. Of the 3,005.7 milliseconds saved, 2,469.6, or 82%, came from the faster boot, by our arithmetic.
These are not new measurements in every case. An EE Times Japan report from July 2025 on the same demonstration chip already gave 2,535.3 and 65.7 milliseconds, and energy from power-on to the first completed AI task of 4.7624 joules for a conventional chip against 0.0942 joules: about 50.6 times less, by our arithmetic. The EE Times Japan report we read did not give the AI-time split or a per-frame energy figure.
Fitting a Model Into 32MB
On-chip memory is small, so the model had to shrink. The team built a hybrid multiplication architecture that combines 16×16, 16×8 and 8×8-bit multiplication, and Mynavi reports that it cut the Tiny YOLOv3 weights from 17.7MB to 9.36MB while keeping 16-bit precision. Detection accuracy, measured as mAP, slipped from 0.325 to 0.316.
Mynavi and The Register both describe that as a 53% reduction. By our arithmetic, 9.36MB is 52.9% of 17.7MB, a cut of about 47%. The compressed weights fill about 29% of the 32MB of MRAM, which also holds the OS, also by our arithmetic.
The chip also reuses the same kernel weights across several clock cycles within a 4×4 tile, a weight-sharing method that, according to Mynavi, reduces data transfer and local memory bandwidth. In the conventional set-up, 12MB of weights had to be moved from the SSD to DRAM before AI processing could start.
What Dan Nystedt Flagged on X
Semiconductor writer Dan Nystedt flagged the chip on X on 3 November. He described the stored OS as “a compact Linux boot image” and wrote that “TSMC manufactures the chip”. The Tohoku release we read does not name the foundry; the July 2025 EE Times Japan report says the demonstration chip was made on TSMC’s 16nm FinFET process with embedded MRAM.
He called it a “Nice real-silicon demo of near-memory computing for edge AI” and listed automotive cameras, sensor fusion and always-ready devices as uses. He also added a caveat: “Not revolutionary: Others โ Hailo, Ambarella, Renesas, etc. โ already use large on-chip SRAM, embedded MRAM, or in-package DRAM”.
Nystedt also noted that the chip keeps on-chip SRAM for feature maps and a DDR interface, so external memory can still be attached for larger models. The release itself does not give a price, a production date or a customer.
AISIN, according to The Register, argues that existing chips rely on external memory to store AI models and generate heavy traffic between processor and model. The same report says AISIN “hasn’t said if or when it can get this chip into production”.
Business Pill · The Memory Wall
An evergreen Business Engineer explainer on the memory wall: why a faster AI chip is not faster AI when data has to move. It teaches the general idea only and does not discuss Tohoku University, AISIN or this chip.
As we read the release, the design trades capacity for latency: 32MB of on-chip MRAM is enough for the OS and a Tiny YOLOv3 model squeezed to 9.36MB, but Nystedt notes the chip keeps a DDR interface for larger models, so external memory remains an option rather than a requirement.
As we read it, the 1/50 energy figure and the 65.7 millisecond boot point at cold-start-heavy uses, the automotive cameras, sensor fusion and always-ready devices Nystedt lists, where a device sleeps and wakes often.
As we read the sources, the measurements are not all new: EE Times Japan reported the 2,535.3 and 65.7 millisecond boot times for the same demonstration chip in July 2025; the EE Times Japan report we read did not give the AI-time split or a per-frame energy figure.
FOR AISIN The Register reports that AISIN has not said if or when the chip could go into production; Mynavi reports that Tohoku and AISIN aim to extend it to cars, robots, industrial equipment and sensing devices.
FOR MEMORY SUPPLIERS Tohoku says the demonstrated AI processing needs no external DRAM or SSD; Nystedt notes the chip still has a DDR interface for larger models.
FOR TSMC EE Times Japan reported in July 2025 that the demonstration chip was made on TSMC’s 16nm FinFET process with embedded MRAM; the 2026 release does not name the foundry.
The framework puts it this way: “Memory is becoming the new compute. HBM growth is outpacing accelerator demand, making memory the rate-limiting factor in the AI scaling equation.”
As we read it, the Tohoku and AISIN figures show the same constraint at the edge rather than in the data centre: the conventional design spent most of its start-up time moving data out of memory, not computing. The framework discusses HBM in data-centre AI and does not discuss this chip, MRAM or AISIN.
What Is Not Established
We read Tohoku University’s web release in Japanese; the full PDF release and the A-SSCC paper were not readable to us, so the conventional baselines (2,535.3 and 594.6 milliseconds), the Arm cores, the 17.7MB-to-9.36MB figures and the mAP values are as reported by Mynavi TECH+. The release does not name the foundry or the conventional chip used for comparison, and gives no conventional per-frame energy.
The 124.2-millisecond and 3,129.9-millisecond totals are our sums of the reported boot and AI times. English renderings of Japanese text are our translations. We did not contact Tohoku University, AISIN or TSMC.
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In the reported figures, the AI accelerator was never the main wait: 81% of the conventional design’s time from power-on to a first detection went to booting the OS from external memory, by our arithmetic. Putting the OS and a 9.36MB model into 32MB of on-chip MRAM cut that boot to 65.7 milliseconds, on a research chip with no announced production plan.
A note on sourcing. We read Tohoku University’s Japanese web release of 2 November 2026; the PDF release and the A-SSCC paper were not readable to us, so conventional-design baselines and some chip details are as reported by Mynavi TECH+. The foundry is as reported by EE Times Japan (July 2025) and by Dan Nystedt. English renderings of Japanese text are our translations. Totals, shares and ratios are our arithmetic. We did not contact Tohoku University, AISIN or TSMC.
Gennaro Cuofano is a CRO and tech executive who has worked in AI since late 2015, starting with bringing NLP, natural-language generation, voice and chatbot products to the marketing industry. His background is in law and finance: he holds a Master's degree in Law and an International MBA with an emphasis on corporate finance (LUISS Business School and the University of San Diego, 2012), and worked as a financial analyst at a real-estate investment firm in San Diego and as an assistant controller. His work focuses on business model strategy, business engineering and, more broadly, structural analysis: how companies make money, read from their own filings. He created FourWeekMBA and leads research there and at The Business Engineer, his newsletter on AI and business strategy, with over 95,000 subscribers and more than 1,000 published analyses. His writing has also appeared on Entrepreneur (for example, How to Digitize a Family Business in Europe) and HackerNoon. Find him on LinkedIn and Substack. See how we source.
