Waymo Builds Its First Custom Chip — A 5nm ASIC for Sensor Fusion, While Keeping Nvidia and AMD for the Rest

Waymo’s first custom silicon — announced alongside its Ojai robotaxi platform and reported by Bloomberg — is a targeted ASIC for one latency-critical job, not a break from merchant chips.

What Happened

According to Waymo’s own announcement and Bloomberg’s reporting, Waymo has built and deployed its first custom application-specific integrated circuit — a 5-nanometer chip manufactured by TSMC, rated at approximately 1,000 trillion operations per second. The chip does one thing: it takes the simultaneous torrent of camera, lidar, and radar data streaming off a driverless car and fuses that sensor data in real time before passing a clean, unified picture to the driving software. The stated goal is latency — sharper, faster perception in dense urban traffic, where milliseconds of delay are a safety variable, not a performance preference. The chip arrived alongside Waymo’s next-generation robotaxi platform, which the company calls Ojai.

The most important fact in the announcement is what Waymo explicitly did not do. The company was unambiguous: it continues to work with AMD, Nvidia, Micron, Samsung, SanDisk, Socionext, and TSMC, pairing the new ASIC with third-party CPUs, GPUs, and accelerators across the rest of its computing stack. The custom chip handles sensor fusion; the merchant ecosystem handles everything else. This is addition, not substitution.

It is also worth noting that custom silicon in autonomous vehicles is an established practice, not a new frontier. Tesla shipped its own Full Self-Driving chip in 2019. Waymo is joining a pattern that already exists, not inventing one. The performance and safety gains cited — faster reactions, sharper perception — are Waymo’s own claims as stated in its announcement; they have not been independently measured or externally verified.

The Structural Read

What Waymo did is the custom-silicon-for-the-hot-path pattern, and it is consistent everywhere it appears. The logic runs like this: when a workload is fixed in shape, high in volume, and sensitive to latency or cost, a chip designed for exactly that workload beats a general-purpose GPU on efficiency — and the volume amortizes the considerable cost of designing it. Google built the TPU for matrix multiplication in inference. Amazon built Trainium for training at cloud scale. Microsoft built Maia for its own inference stack. Tesla built the FSD chip for driving-neural-net inference. Now Waymo has built an ASIC for sensor fusion. Each move follows the same economic logic; only the workload changes.

Sensor fusion in an autonomous vehicle is a textbook case for a custom chip. The pipeline is well-defined and does not change week to week. It runs constantly — every second, in every vehicle, in every city. And its latency is safety-critical in a way that most compute workloads are not: a slower perception loop is not a user-experience issue, it is a braking-distance issue. Those three properties — fixed shape, high volume, safety-critical latency — are exactly the conditions under which the economics of a custom ASIC clear the bar. The push toward purpose-built silicon for physical-AI pipelines is the broader structural shift this fits inside.

What makes the move analytically interesting, though, is the restraint surrounding it. Waymo did not attempt to replace the flexible, general-purpose compute layer where merchant GPUs still have a structural advantage. It kept Nvidia and AMD for that. That restraint is the tell: this is a custom-plus-merchant hybrid, and hybrids are the durable pattern across every large AI operator that has gone this route. No one has ripped the merchant stack out entirely, because the merchant stack is where adaptability lives.

That framing cuts directly against the louder narrative that startups pitch as chip-agnostic orchestration layers designed to “break the Nvidia monoculture.” Waymo’s answer is quieter and more precise: you do not break the monoculture by swapping the whole stack — you erode it selectively, taking the specific workloads whose economics justify custom silicon and leaving the merchant ecosystem to do what it does best everywhere else. The merchant-chip floor remains. The custom layer grows on top of it, task by task. Both Beyond Nvidia’s Moat and The Map of AI Redrawn trace this exact structural dynamic across the stack.

Three Implications

The Bottom Line

Waymo’s first custom chip is a real and meaningful piece of engineering — a 5nm ASIC from TSMC, purpose-built for the sensor-fusion loop where latency is a safety variable — and it belongs to a well-established pattern that Google, Amazon, Microsoft, and Tesla have all run before it. What it is not is a break from merchant silicon, a threat to Nvidia’s core business, or a landmark of vertical integration; Waymo said explicitly that Nvidia, AMD, and the rest of the supplier roster stay in place for everything outside the hot path. The durable insight is the one that cuts against the louder noise: large AI operators do not escape merchant-chip dependence by replacing the stack, they erode it selectively — one fixed, high-volume, latency-critical workload at a time — and this is one of those workloads.

Sources: Waymo Blog — “Look Under Our Trunk” (August 2026) · Business Engineer — Beyond Nvidia’s Moat · Business Engineer — The Map of AI Redrawn · FourWeekMBA — Microsoft Maia and the Hyperscaler Silicon Race · FourWeekMBA — Sony, TSMC, and the Physical-AI Sensor Stack · Bloomberg reporting on Waymo’s Ojai platform announcement.